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1. general description the sc16c554b/554db is a 4-channel universal asynchronous receiver and transmitter (quart) used for serial data communications. its principal function is to convert parallel data into serial data and vice versa. the uart can handle serial data rates up to 5 mbit/s. it comes with an intel or motorola interface. the sc16c554b/554db is pin compatible with the st16c554 and tl16c554 and it will power-up to be functionally equivalent to the 16c454. programming of control registers enables the added features of the sc16c554b/554db. some of these added features are the 16-byte receive and transmit fifos, four receive trigger levels. the sc16c554b/554db also provides dma mode data transfers through fifo trigger levels and the txrd y and rxrd y signals. ( txrd y and rxrd y signals are not available in the hvqfn48 package.) on-board status registers provide the user with error indications, operational status, and modem interface control. system interrupts may be tailored to meet user requirements. an internal loop-back capability allows on-board diagnostics. the sc16c554b/554db operates at 5 v, 3.3 v and 2.5 v, and the industrial temperature range, and is available in plastic plcc68, lqfp64, lqfp80, and hvqfn48 packages. on the hvqfn48 package only, channel c has all the modem pins. channels a and b have only r ts and cts pins and channel d does not have any modem pin. 2. features n 4 channel uart n 5 v, 3.3 v and 2.5 v operation n industrial temperature range ( - 40 c to +85 c) n the sc16c554b is pin and software compatible with the industry-standard st16c454/554, st68c454/554, st16c554, tl16c554 n the sc16c554db is pin and software compatible with st16c554d, and software compatible with st16c454/554, st16c554, tl16c554 n up to 5 mbit/s data rate at 5 v and 3.3 v, and 3 mbit/s at 2.5 v n 5 v tolerant inputs n 16-byte transmit fifo n 16-byte receive fifo with error ?ags n programmable auto- r ts and auto- cts u in auto- cts mode, cts controls transmitter u in auto- r ts mode, rxfifo contents and threshold control r ts n automatic hardware ?ow control ( r ts/ cts) n software selectable baud rate generator sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos rev. 03 1 september 2005 product data sheet
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 2 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos n four selectable receive fifo interrupt trigger levels n standard modem interface n standard asynchronous error and framing bits (start, stop, and parity overrun break) n transmit, receive, line status, and data set interrupts independently controlled n fully programmable character formatting: u 5-bit, 6-bit, 7-bit, or 8-bit characters u even, odd, or no-parity formats u 1, 1 1 2 , or 2-stop bit u baud generation (dc to 5 mbit/s) n false start-bit detection n complete status reporting capabilities n 3-state output ttl drive capabilities for bidirectional data bus and control bus n line break generation and detection n internal diagnostic capabilities: u loop-back controls for communications link fault isolation n prioritized interrupt system controls n modem control functions ( cts, r ts, dsr, dtr, ri, cd). 3. ordering information table 1: ordering information type number package name description version sc16c554bib64 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 sc16c554bib80 lqfp80 plastic low pro?le quad ?at package; 80 leads; body 12 12 1.4 mm sot315-1 sc16c554bibm lqfp64 plastic low pro?le quad ?at package; 64 leads; body 7 7 1.4 mm sot414-1 sc16c554bibs hvqfn48 plastic thermal enhanced very thin quad ?at package; no leads; 48 terminals; body 6 6 0.85 mm sot778-3 sc16c554dbia68 plcc68 plastic leaded chip carrier; 68 leads sot188-2 sc16c554dbib64 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 3 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 4. block diagram fig 1. block diagram of sc16c554b/554db (16 mode) dtra to dtrd rtsa to rtsd transmit fifo registers txa to txd receive shift register receive fifo registers rxa to rxd interconnect bus lines and control signals sc16c554b/554db transmit shift register xtal2 xtal1 002aaa877 intsel flow control logic clksel 16/68 data b u s and control logic register select logic interrupt control logic d0 to d7 ior iow reset a0 to a2 csa to csd inta to intd txrdy rxrdy clock and baud rate generator modem control logic ctsa to ctsd ria to rid cda to cdd dsra to dsrd flow control logic
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 4 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 2. block diagram of sc16c554b/554db (68 mode) dtra to dtrd rtsa to rtsd transmit fifo registers txa to txd receive shift register receive fifo registers rxa to rxd interconnect bus lines and control signals sc16c554b/554db transmit shift register xtal2 xtal1 002aaa878 flow control logic clksel 16/68 data b u s and control logic register select logic interrupt control logic d0 to d7 r/w reset a0 to a4 cs irq txrdy rxrdy clock and baud rate generator modem control logic ctsa to ctsd ria to rid cda to cdd dsra to dsrd flow control logic
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 5 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 5. pinning information 5.1 pinning 5.1.1 plcc68 fig 3. pin con?guration for plcc68 (16 mode) sc16c554dbia68 16 mode dsra dsrd ctsa ctsd dtra dtrd v cc gnd rtsa rtsd inta intd csa csd txa txd iow ior txb txc csb intb rtsb gnd dtrb ctsb dsrb csc intc rtsc v cc dtrc ctsc dsrc cdb gnd rib d7 rxb d6 v cc d5 cda ria rxa n.c. d4 a2 d3 a1 d2 a0 d1 xtal1 d0 xtal2 intsel reset rxrdy txrdy gnd rxc ric cdc v cc rxd rid cdd 002aaa879 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 21 22 23 24 25 26 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 6 5 4 3 2 1 68 67 66 65 64 9 8 7 38 39 40 41 42 43 63 62 61
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 6 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 4. pin con?guration for plcc68 (68 mode) sc16c554dbia68 68 mode dsra dsrd ctsa ctsd dtra dtrd v cc gnd rtsa rtsd irq n.c. cs n.c. txa txd r/w n.c. txb txc a3 n.c. rtsb gnd dtrb ctsb dsrb a4 n.c. rtsc v cc dtrc ctsc dsrc cdb gnd rib d7 rxb d6 v cc d5 cda ria rxa 16/68 d4 a2 d3 a1 d2 a0 d1 xtal1 d0 xtal2 n.c. reset rxrdy txrdy gnd rxc ric cdc v cc rxd rid cdd 002aaa880 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 21 22 23 24 25 26 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 6 5 4 3 2 1 68 67 66 65 64 9 8 7 38 39 40 41 42 43 63 62 61
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 7 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 5.1.2 lqfp64 fig 5. pin con?guration for lqfp64 sc16c554bib64 sc16c554dbib64 sc16c554bibm intd csd txd ior txc csc intc dsrc 002aaa881 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 dsra ctsa dtra v cc rtsa inta csa txa iow txb csb intb rtsb gnd dtrb ctsb dsrb cdb rib rxb v cc a2 a1 a0 xtal1 xtal2 reset gnd rxc ric cdc dsrd ctsd dtrd gnd rtsd rtsc v cc dtrc ctsc gnd d7 d6 d5 cda ria rxa d4 d3 d2 d1 d0 v cc rxd rid cdd
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 8 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 5.1.3 lqfp80 fig 6. pin con?guration for lqfp80 sc16c554bib80 n.c. cdc ric rxc gnd txrdy d0 rxrdy d1 reset d2 n.c. n.c. xtal2 d3 xtal1 d4 n.c. d5 d6 d7 gnd rxa ria cda n.c. n.c. n.c. n.c. dsrd ctsd dtrd gnd rtsd intd csd txd n.c. n.c. ior txc csc intc rtsc v cc dtrc ctsc dsrc n.c. n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 002aaa882 n.c. cdd rid rxd v cc intsel dsra ctsa dtra v cc rtsa inta csa txa iow txb csb intb rtsb gnd dtrb ctsb dsrb cdb rib rxb v cc a2 a1 a0
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 9 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 5.1.4 hvqfn48 fig 7. pin con?guration for hvqfn (16 mode) fig 8. pin con?guration for hvqfn (68 mode) 002aab552 sc16c554bibs 16 mode transparent top view dsrc ctsb ctsc intb dtrc csb v cc txb rtsc iow intc txa csc csa txc inta ior rtsa txd v cc csd ctsa intd rxb 16/68 a2 a1 a0 xtal1 xtal2 reset gnd rxc ric cdc rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 rxd gnd 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 terminal 1 index area rtsb 002aab554 sc16c554bibs 68 mode transparent top view dsrc ctsb ctsc n.c. dtrc a3 v cc txb rtsc r/w n.c. txa a4 cs txc irq ior rtsa txd v cc csd ctsa n.c. rxb 16/68 a2 a1 a0 xtal1 xtal2 reset gnd rxc ric cdc rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 rxd gnd 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 terminal 1 index area rtsb
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 10 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 5.2 pin description table 2: pin description symbol pin type description plcc68 lqfp64 lqfp80 hvqfn48 16/ 68 31 - - 14 i 16/68 interface type select (input with internal pull-up). this input provides the 16 (intel) or 68 (motorola) bus interface type select. the functions of ior, io w, inta to intd, and csa to csd are re-assigned with the logical state of this pin. when this pin is a logic 1, the 16 mode interface (16c554) is selected. when this pin is a logic 0, the 68 mode interface (68c554) is selected. when this pin is a logic 0, io w is re-assigned to r/ w, reset is re-assigned to reset, ior is not used, and inta to intd are connected in a wire-or con?guration. the wire-or outputs are connected internally to the open drain irq signal output. this pin is not available on 64-pin packages which operate in the 16 mode only. a0 34 24 48 17 i address 0 select bit. internal registers address selection in 16 and 68 modes. a1 33 23 47 16 i address 1 select bit. internal registers address selection in 16 and 68 modes. a2 32 22 46 15 i address 2 select bit. internal registers address selection in 16 and 68 modes. a3 20 - - 9 i address 3 to address 4 select bits. when the 68 mode is selected, these pins are used to address or select individual uarts (providing cs is a logic 0). in the 16 mode, these pins are re-assigned as chip selects, see csb and csc. a4 50 - - 31 cd a 9 64 19 - i carrier detect (active low). these inputs are associated with individual uart channels a through d. a logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. cdb 27 18 42 - cdc 43 31 59 24 cdd 61 49 2 - cs 16 - - 5 i chip select (active low). in the 68 mode, this pin functions as a multiple channel chip enable. in this case, all four uarts (a to d) are enabled when the cs pin is a logic 0. an individual uart channel is selected by the data contents of address bits a3 to a4. when the 16 mode is selected (68-pin devices), this pin functions as csa (see de?nition under csa, csb). csa 16 7 28 5 i chip select a, b, c, d (active low). this function is associated with the 16 mode only, and for individual channels a through d. when in 16 mode, these pins enable data transfers between the user cpu and the sc16c554b/554db for the channel(s) addressed. individual uart sections (a, b, c, d) are addressed by providing a logic 0 on the respective csa to csd pin. when the 68 mode is selected, the functions of these pins are re-assigned. 68 mode functions are described under their respective name/pin headings. csb 20 11 33 9 csc 50 38 68 31 csd 54 42 73 35
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 11 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos ctsa 11 2 23 1 i clear to send (active low). these inputs are associated with individual uart channels a to d. a logic 0 on the cts pin indicates the modem or data set is ready to accept transmit data from the sc16c554b/554db. status can be tested by reading msr[4]. this pin only affects the transmit or receive operations when auto- cts function is enabled via mcr[5] for hardware ?ow control operation. ctsb 25 16 38 12 ctsc 45 33 63 26 ctsd 59 47 78 - d0 to d2, d3 to d7 66 to 68, 1to5 53 to 55, 56 to 60 7to9, 11 to 15 39 to 41, 42 to 46 i/o data bus (bidirectional). these pins are the 8-bit, 3-state data bus for transferring information to or from the controlling cpu. d0 is the least signi?cant bit and the ?rst data bit in a transmit or receive serial data stream. dsra 10 1 22 - i data set ready (active low). these inputs are associated with individual uart channels, a through d. a logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the uart. this pin has no effect on the uarts transmit or receive operation. dsrb 26 17 39 - dsrc 44 32 62 25 dsrd 60 48 79 - dtra 12 3 24 - o data terminal ready (active low). these outputs are associated with individual uart channels, a through d. a logic 0 on this pin indicates that the sc16c554b/554db is powered-on and ready. this pin can be controlled via the modem control register. writing a logic 1 to mcr[0] will set the dtr output to logic 0, enabling the modem. this pin will be a logic 1 after writing a logic 0 to mcr[0], or after a reset. this pin has no effect on the uarts transmit or receive operation. dtrb 24 15 37 - dtrc 46 34 64 27 dtrd 58 46 77 - gnd 6, 23, 40, 57 14, 28, 45, 61 16, 36, 56, 76 21, 37, 47 i signal and power ground. inta 15 6 27 4 o interrupt a, b, c, d (active high). this function is associated with the 16 mode only. these pins provide individual channel interrupts inta to intd. inta to intd are enabled when mcr[3] is set to a logic 1, interrupts are enabled in the interrupt enable register (ier), and when an interrupt condition exists. interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status ?ag is detected. when the 68 mode is selected, the functions of these pins are re-assigned. 68 mode functions are described under their respective name/pin headings. intb 21 12 34 10 intc 49 37 67 30 intd 55 43 74 36 table 2: pin description continued symbol pin type description plcc68 lqfp64 lqfp80 hvqfn48
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 12 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos intsel 65 - 6 - i interrupt select (active high, with internal pull-down). this function is associated with the 16 mode only. when the 16 mode is selected, this pin can be used in conjunction with mcr[3] to enable or disable the 3-state interrupts, inta to intd, or override mcr[3] and force continuous interrupts. interrupt outputs are enabled continuously by making this pin a logic 1. making this pin a logic 0 allows mcr[3] to control the 3-state interrupt output. in this mode, mcr[3] is set to a logic 1 to enable the 3-state outputs. this pin is disabled in the 68 mode. due to pin limitations on the 64-pin packages, this pin is not available. to cover this limitation, the sc16c554dbib64 version operates in the continuous interrupt enable mode by bonding this pin to v cc internally. the sc16c554bib64 operates with mcr[3] control by bonding this pin to gnd. the intsel pin is not available on the hvqfn48 package. ior 52 40 70 33 i input/output read strobe (active low). this function is associated with the 16 mode only. a logic 0 transition on this pin will load the contents of an internal register de?ned by address bits a0 to a2 onto the sc16c554b/554db data bus (d0 to d7) for access by external cpu. this pin is disabled in the 68 mode. io w189317i input/output write strobe (active low). this function is associated with the 16 mode only. a logic 0 transition on this pin will transfer the contents of the data bus (d0 to d7) from the external cpu to an internal register that is de?ned by address bits a0 to a2. when the 68 mode is selected, this pin functions as r/ w (see de?nition under r/ w). irq 15 - - 4 o interrupt request or interrupt a. this function is associated with the 68 mode only. in the 68 mode, interrupts from uart channels a to d are wire-ored internally to function as a single irq interrupt. this pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a uart channel(s) requires service. individual channel interrupt status can be determined by addressing each channel through its associated internal register, using cs and a3 to a4. in the 68 mode, and external pull-up resistor must be connected between this pin and v cc . the function of this pin changes to inta when operating in the 16 mode (see de?nition under inta). n.c. 21, 49, 52, 54, 55, 65 - 1, 10, 20, 21, 30, 40, 41, 49, 52, 60, 61, 71, 80 - - not connected table 2: pin description continued symbol pin type description plcc68 lqfp64 lqfp80 hvqfn48
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 13 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos reset (reset) 37 27 53 20 i reset. in the 16 mode, a logic 1 on this pin will reset the internal registers and all the outputs. the uart transmitter output and the receiver input will be disabled during reset time. (see section 7.10 sc16c554b/554db e xter nal reset conditions for initialization details.) when 16/ 68 is a logic 0 (68 mode), this pin functions similarly, bus as an inverted reset interface signal, reset. ria 8 63 18 - i ring indicator (active low). these inputs are associated with individual uart channels, a to d. a logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. a logic 1 transition on this input pin will generate an interrupt. rib 28 19 43 - ric 42 30 58 23 rid 62 50 3 - r tsa 14 5 26 3 o request to send (active low). these outputs are associated with individual uart channels, a to d. a logic 0 on the r ts pin indicates the transmitter has data ready and waiting to send. writing a logic 1 in the modem control register mcr[1] will set this pin to a logic 0, indicating data is available. after a reset this pin will be set to a logic 1. this pin only affects the transmit and receive operations when auto- r ts function is enabled via mcr[5] for hardware ?ow control operation. r tsb 22 13 35 11 r tsc 48 36 66 29 r tsd 56 44 75 - r/ w18--7i read/write strobe. this function is associated with the 68 mode only. this pin provides the combined functions for read or write strobes. logi c 1 = read from uart register selected by cs and a0 to a4. logi c0=wr ite to uart register selected by cs and a0 to a4. rxa 7 62 17 48 i receive data input rxa to rxd. these inputs are associated with individual serial channel data to the sc16c554b/554db. the rx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. during the local loop-back mode, the rx input pin is disabled and tx data is connected to the uart rx input internally. rxb 29 20 44 13 rxc 41 29 57 22 rxd 63 51 4 38 rxrd y38 - 54- o receive ready (active low). rxrd y contains the wire-ored status of all four receive channel fifos, rxrdya to rxrdyd. a logic 0 indicates receive data ready status, that is, the rhr is full, or the fifo has one or more rx characters available for unloading. this pin goes to a logic 1 when the fifo/rhr is empty, or when there are no more characters available in either the fifo or rhr. individual channel rx status is read by examining individual internal registers via cs and a0 to a4 pin functions. the rxrd y pin is not available on the hvqfn48 package. table 2: pin description continued symbol pin type description plcc68 lqfp64 lqfp80 hvqfn48
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 14 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos txa 17 8 29 6 o transmit data a, b, c, d. these outputs are associated with individual serial transmit channel data from the sc16c554b/554db. the tx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. during the local loop-back mode, the tx output pin is disabled and tx data is internally connected to the uart rx input. txb 19 10 32 8 txc 51 39 69 32 txd 53 41 72 34 txrd y39- 55- o transmit ready (active low). txrd y contains the wire-ored status of all four transmit channel fifos, txrdya to txrdyd. a logic 0 indicates a buffer ready status, that is, at least one location is empty and available in one of the tx channels (a to d). this pin goes to a logic 1 when all four channels have no more empty locations in the tx fifo or thr. individual channel tx status can be read by examining individual internal registers via cs and a0 to a4 pin functions. the txrd y pin is not available on the hvqfn48 package. v cc 13, 30, 47, 64 4, 21, 35, 52 5, 25, 45, 65 2, 28 i power supply inputs. xtal1 35 25 50 18 i crystal or external clock input. functions as a crystal input or as an external clock input. a crystal can be connected between this pin and xtal2 to form an internal oscillator circuit (see figure 13 ). alternatively, an external clock can be connected to this pin to provide custom data rates. (see section 6.6 prog r ammab le baud r ate gener ator .) xtal2 36 26 51 19 o output of the crystal oscillator or buffered clock. (see also xtal1.) crystal oscillator output or buffered clock output. table 2: pin description continued symbol pin type description plcc68 lqfp64 lqfp80 hvqfn48
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 15 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 6. functional description the sc16c554b/554db provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character. data integrity is insured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the electronic circuitry to provide all these functions is fairly complex, especially when manufactured on a single integrated silicon chip. the sc16c554b/554db represents such an integration with greatly enhanced features. the sc16c554b/554db is fabricated with an advanced cmos process to achieve low drain power and high speed requirements. the sc16c554b/554db is an upward solution that provides 16 bytes of transmit and receive fifo memory, instead of none in the 16c454. the sc16c554b/554db is designed to work with high speed modems and shared network environments that require fast data processing time. increased performance is realized in the sc16c554b/554db by the larger transmit and receive fifos. this allows the external processor to handle more networking tasks within a given time. in addition, the four selectable levels of fifo trigger interrupt is uniquely provided for maximum data throughput performance, especially when operating in a multi-channel environment. the combination of the above greatly reduces the bandwidth requirement of the external controlling cpu, increases performance, and reduces power consumption. the sc16c554b/554dbai68 combines the package interface modes of the 16c454/554 and 68c454/554 series on a single integrated chip. the 16 mode interface is designed to operate with the intel-type of microprocessor bus, while the 68 mode is intended to operate with motorola and other popular microprocessors. following a reset, the sc16c554b/554dbai68 is downward compatible with the 16c454/554 or the 68c454/554, dependent on the state of the interface mode selection pin, 16/ 68. the sc16c554b/554db is capable of operation to 1.5 mbit/s with a 24 mhz crystal and up to 5 mbit/s with an external clock input (at 3.3 v and 5 v; at 2.5 v the maximum speed is 3 mbit/s). the rich feature set of the sc16c554b/554db is available through internal registers. selectable receive fifo trigger levels, selectable tx and rx baud rates, and modem interface controls are all standard features. in the 16 mode, intsel and mcr[3] can be con?gured to provide a software controlled or continuous interrupt capability. due to pin limitations of the 64-pin package, this feature is offered by two different lqfp64 packages. the sc16c554db operates in the continuous interrupt enable mode by bonding intsel to v cc internally. the sc16c554b operates in conjunction with mcr[3] by bonding intsel to gnd internally.
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 16 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 6.1 interface options two user interface modes are selectable for the plcc68 package. these interface modes are designated as the 16 mode and the 68 mode. this nomenclature corresponds to the early 16c454/554 and 68c454/554 package interfaces respectively. 6.1.1 the 16 mode interface the 16 mode con?gures the package interface pins for connection as a standard 16 series (intel) device and operates similar to the standard cpu interface available on the 16c454/554. in the 16 mode (pin 16/ 68 = logic 1), each uart is selected with individual chip select ( csx) pins, as shown in t ab le 3 . 6.1.2 the 68 mode interface the 68 mode con?gures the package interface pins for connection with motorola, and other popular microprocessor bus types. the interface operates similar to the 68c454/554. in this mode, the sc16c554b/554db decodes two additional addresses, a3 to a4, to select one of the four uart ports. the a3 to a4 address decode function is used only when in the 68 mode (16/ 68 = logic 0), and is shown in t ab le 4 . table 3: serial port channel selection, 16 mode interface csa csb csc csd uart channel 1111 none 0111a 1011b 1101c 1110d table 4: serial port channel selection, 68 mode interface cs a4 a3 uart channel 1 n/a n/a none 000a 001b 010c 011d
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 17 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 6.2 internal registers the sc16c554b/554db provides 12 internal registers for monitoring and control. these registers are shown in t ab le 5 . these registers function as data holding registers (thr/rhr), interrupt status and control registers (ier/isr), a fifo control register (fcr), line status and control registers (lcr/lsr), modem status and control registers (mcr/msr), programmable data rate (clock) control registers (dll/dlm), and a user accessible scratchpad register (spr). register functions are more fully described in the following paragraphs. [1] these registers are accessible only when lcr[7] is a logic 0. [2] these registers are accessible only when lcr[7] is a logic 1. 6.3 fifo operation the 16 byte transmit and receive data fifos are enabled by the fifo control register (fcr) bit 0. with sc16c554b devices, the user can set the receive trigger level, but not the transmit trigger level. the receiver fifo section includes a time-out function to ensure data is delivered to the external cpu. an interrupt is generated whenever the receive holding register (rhr) has not been read following the loading of a character or the receive trigger level has not been reached. table 5: internal registers decoding a2 a1 a0 read mode write mode general register set (thr/rhr, ier/isr, mcr/msr, fcr, lsr, spr) [1] 0 0 0 receive holding register transmit holding register 0 0 1 interrupt enable register interrupt enable register 0 1 0 interrupt status register fifo control register 0 1 1 line control register line control register 1 0 0 modem control register modem control register 1 0 1 line status register n/a 1 1 0 modem status register n/a 1 1 1 scratchpad register scratchpad register baud rate register set (dll/dlm) [2] 0 0 0 lsb of divisor latch lsb of divisor latch 0 0 1 msb of divisor latch msb of divisor latch table 6: flow control mechanism selected trigger level (characters) int pin activation negate r ts assert r ts 1141 4484 8 8 12 8 14 14 14 10
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 18 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 6.4 auto?ow control (see figure 9 ) auto?ow control is comprised of auto- cts and auto- r ts. with auto- cts, the cts input must be active before the transmitter fifo can emit data. with auto- r ts, r ts becomes active when the receiver needs more data and noti?es the sending serial device. when r ts is connected to cts, data transmission does not occur unless the receiver fifo has space for the data; thus, overrun errors are eliminated using uart 1 and uart 2 from a sc16c554b/554db with the auto?ow control enabled. if not, overrun errors occur when the transmit data rate exceeds the receiver fifo read latency. 6.4.1 auto- r ts (see figure 9 ) auto- r ts data ?ow control originates in the receiver timing and control block (see block diagrams in figure 1 and figure 2 ) and is linked to the programmed receiver fifo trigger level. when the receiver fifo level reaches a trigger level of 1, 4, or 8 (see figure 11 ), r ts is de-asserted. with trigger levels of 1, 4, and 8, the sending uart may send an additional byte after the trigger level is reached (assuming the sending uart has another byte to send) because it may not recognize the de-assertion of r ts until after it has begun sending the additional byte. r ts is automatically reasserted once the rx fifo is emptied by reading the receiver buffer register. when the trigger level is 14 (see figure 12 ), r ts is de-asserted after the ?rst data bit of the 16th character is present on the rx line. r ts is reasserted when the rx fifo has at least one available byte space. remark: auto- r ts is not supported in channel d of the hvqfn48 package, therefore mcr[5] of channel d should not be written. 6.4.2 auto- cts (see figure 9 ) the transmitter circuitry checks cts before sending the next data byte. when cts is active, it sends the next byte. to stop the transmitter from sending the following byte, cts must be released before the middle of the last stop bit that is currently being sent (see figure 10 ). the auto- cts function reduces interrupts to the host system. when ?ow control is enabled, cts level changes do not trigger host interrupts because the device automatically controls its own transmitter. without auto- cts, the transmitter sends any data present in the transmit fifo and a receiver overrun error may result. fig 9. auto?ow control (auto- r ts and auto- cts) example rcv fifo serial to parallel flow control xmt fifo parallel to serial flow control parallel to serial flow control serial to parallel flow xmt fifo rcv fifo ace1 ace2 d7 to d0 rx tx rts cts tx rx d7 to d0 control 002aaa048 cts rts
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 19 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos remark: auto- cts is not supported in channel d of the hvqfn48 package, therefore mcr[5] of channel d should not be written. 6.4.3 enabling auto?ow control and auto- cts auto?ow control is enabled by setting mcr[5] and mcr[1]. 6.4.4 auto- cts and auto- r ts functional timing the receiver fifo trigger level can be set to 1 byte, 4 bytes, 8 bytes, or 14 bytes. these are described in figure 11 and figure 12 . table 7: enabling auto?ow control and auto- cts mcr[5] mcr[1] selection 1 1 auto r ts and cts 1 0 auto cts 0 x disable (1) when cts is low, the transmitter keeps sending serial data out. (2) if cts goes high before the middle of the last stop bit of the current byte, the transmitter ?nishes sending the current byte, but is does not send the next byte. (3) when cts goes from high to low, the transmitter begins sending data again. fig 10. cts functional timing waveforms start bits 0 to 7 stop tx cts 002aaa049 start bits 0 to 7 stop start bits 0 to 7 stop (1) n = rcv fifo trigger level (1 byte, 4 bytes, or 8 bytes). (2) the two blocks in dashed lines cover the case where an additional byte is sent as described in section 6.4.1 fig 11. r ts functional timing waveforms, rcv fifo trigger level = 1 byte, 4 bytes, or 8 bytes start byte n start byte n + 1 start byte stop stop stop rx rts ior (rd rbr) n n + 1 12 002aaa050
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 20 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 6.5 hardware/software and time-out interrupts following a reset, if the transmitter interrupt is enabled, the sc16c554b/554db will issue an interrupt to indicate that the transmit holding register is empty. this interrupt must be serviced prior to continuing operations. the lsr register provides the current singular highest priority interrupt only. only after servicing the higher pending interrupt will the lower priority interrupt(s) be re?ected in the status register. servicing the interrupt without investigating further interrupt conditions can result in data errors. when two interrupt conditions have the same priority, it is important to service these interrupts correctly. receive data ready and receive time out have the same interrupt priority (when enabled by ier[0]). the receiver issues an interrupt after the number of characters have reached the programmed trigger level. in this case, the sc16c554b/554db fifo may hold more characters than the programmed trigger level. following the removal of a data byte, the user should re-check lsr[0] for additional characters. a receive time out will not occur if the receive fifo is empty. the time-out counter is reset at the center of each stop bit received or each time the receive holding register (rhr) is read. the actual time-out value is 4 character time. in the 16 mode for the plcc68 package, the system/board designer can optionally provide software controlled 3-state interrupt operation. this is accomplished by intsel and mcr[3]. when intsel interface pin is left open or made a logic 0, mcr[3] controls the 3-state interrupt outputs, inta to intd. when intsel is a logic 1, mcr[3] has no effect on the inta to intd outputs, and the package operates with interrupt outputs enabled continuously. 6.6 programmable baud rate generator the sc16c554b/554db supports high speed modem technologies that have increased input data rates by employing data compression schemes. for example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. a 128.0 kbit/s isdn modem that supports data compression may need an input data rate of 460.8 kbit/s. (1) r ts is de-asserted when the receiver receives the ?rst data bit of the sixteenth byte. the receive fifo is full after ?nishing the sixteenth byte. (2) r ts is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is more than one byte of space available. (3) when the receive fifo is full, the ?rst receive buffer register read re-asserts r ts. fig 12. r ts functional timing waveforms, rcv fifo trigger level = 14 bytes byte 14 byte 15 rx rts ior (rd rbr) start byte 18 stop start byte 16 stop 002aaa051 rts released after the first data bit of byte 16
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 21 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos a single baud rate generator is provided for the transmitter and receiver, allowing independent tx/rx channel control. the programmable baud rate generator is capable of accepting an input clock up to 80 mhz (for 3.3 v and 5 v operation), as required for supporting a 5 mbit/s data rate. the sc16c554b/554db can be con?gured for internal or external clock operation. for internal clock oscillator operation, an industry standard microprocessor crystal (parallel resonant/22 pf to 33 pf load) is connected externally between the xtal1 and xtal2 pins (see figure 13 ). alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates (see t ab le 8 ). programming the baud rate generator registers dlm (msb) and dll (lsb) provides a user capability for selecting the desired ?nal baud rate. fig 13. crystal oscillator connection table 8: baud rate generator programming table using a 7.3728 mhz clock output baud rate (bit/s) user 16 clock divisor dlm program value (hex) dll program value (hex) decimal hex 200 2304 900 09 00 1200 384 180 01 80 2400 192 c0 00 c0 4800 96 60 00 60 9600 48 30 00 30 19.2 k 24 18 00 18 38.4 k 12 0c 00 0c 76.8 k 6 06 00 06 153.6 k 3 03 00 03 230.4 k 2 02 00 02 460.8 k 1 01 00 01 002aaa870 c2 47 pf xtal1 xtal2 x1 1.8432 mhz c1 22 pf c2 33 pf xtal1 xtal2 1.5 k w x1 1.8432 mhz c1 22 pf
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 22 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 6.7 dma operation the sc16c554b/554db fifo trigger level provides additional ?exibility to the user for block mode operation. lsr[5:6] provide an indication when the transmitter is empty or has an empty location(s). the user can optionally operate the transmit and receive fifos in the dma mode (fcr[3]). when the transmit and receive fifos are enabled and the dma mode is de-activated (dma mode 0), the sc16c554b/554db activates the interrupt output pin for each data transmit or receive operation. when dma mode is activated (dma mode 1), the user takes the advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the preset trigger level. in this mode, the sc16c554b/554db sets the interrupt output pin when the characters in the receive fifos are above the receive trigger level. remark: dma operation is not supported in the hvqfn48 package. 6.8 loop-back mode the internal loop-back capability allows on-board diagnostics. in the loop-back mode, the normal modem interface pins are disconnected and recon?gured for loop-back internally. mcr[0:3] register bits are used for controlling loop-back diagnostic testing. in the loop-back mode, op1 and op2 in the mcr register (bits 2:3) control the modem ri and cd inputs, respectively. mcr signals dtr and r ts (bits 0:1) are used to control the modem dsr and cts inputs, respectively. the transmitter output (tx) and the receiver input (rx) are disconnected from their associated interface pins, and instead are connected together internally (see figure 14 ). the cts, dsr, cd, and ri are disconnected from their normal modem control input pins, and instead are connected internally to r ts, dtr, op2 and op1. loop-back test data is entered into the transmit holding register via the user data bus interface, d0 to d7. the transmit uart serializes the data and passes the serial data to the receive uart via the internal loop-back connection. the receive uart converts the serial data back into parallel data that is then made available at the user data interface d0 to d7. the user optionally compares the received data to the initial transmitted data for verifying error-free operation of the uart tx/rx circuits. in this mode, the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational. however, the interrupts can only be read using lower four bits of the modem status register (msr[0:3]) instead of the four modem status register bits 4:7. the interrupts are still controlled by the ier.
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 23 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 14. internal loop-back mode diagram (16 mode) ctsa to ctsd transmit fifo registers txa to txd receive shift register receive fifo registers rxa to rxd interconnect bus lines and control signals sc16c554b/554db transmit shift register xtal2 xtal1 002aaa883 flow control logic data b u s and control logic register select logic interrupt control logic d0 to d7 ior iow reset a0 to a2 csa to csd inta to intd txrdy rxrdy clock and baud rate generator modem control logic flow control logic rtsa to rtsd dsra to dsrd dtra to dtrd ria to rid op1a to op1d cda to cdd op2a to op2d mcr[4] = 1
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 24 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 15. internal loop-back mode diagram (16 mode) for hvqfn48 package ctsa to ctsc transmit fifo registers txa to txd receive shift register receive fifo registers rxa to rxd interconnect bus lines and control signals sc16c554b/554db (hvqfn48) transmit shift register xtal2 xtal1 002aab553 flow control logic data b u s and control logic register select logic interrupt control logic d0 to d7 ior iow reset a0 to a2 csa to csd inta to intd clock and baud rate generator modem control logic flow control logic rtsa to rtsc dsrc dtrc ric op1c cdc op2c mcr[4] = 1
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 25 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 16. internal loop-back mode diagram (68 mode) ctsa to ctsd transmit fifo registers txa to txd receive shift register receive fifo registers rxa to rxd interconnect bus lines and control signals sc16c554b/554db transmit shift register xtal2 xtal1 002aaa884 flow control logic data b u s and control logic register select logic interrupt control logic d0 to d7 r/w reset a0 to a4 cs irq txrdy rxrdy clock and baud rate generator modem control logic flow control logic rtsa to rtsd dsra to dsrd dtra to dtrd ria to rid op1a to op1d cda to cdd op2a to op2d mcr[4] = 1 16/68
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 26 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 17. internal loop-back mode diagram (68 mode) for hvqfn48 package ctsc transmit fifo registers txa to txd receive shift register receive fifo registers rxa to rxd interconnect bus lines and control signals sc16c554b/554db (hvqfn48) transmit shift register xtal2 xtal1 002aab555 flow control logic data b u s and control logic register select logic interrupt control logic d0 to d7 r/w reset a0 to a4 cs irq clock and baud rate generator modem control logic flow control logic rtsc dsrc dtrc ric op1c cdc op2c mcr[4] = 1 16/68
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 27 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 7. register descriptions t ab le 9 details the assigned bit functions for the sc16c554b/554db internal registers. the assigned bit functions are more fully de?ned in section 7.1 through section 7.10 . [1] the value shown represents the registers initialized hex value; x = not applicable. [2] these registers are accessible only when lcr[7] = 0. [3] this function is not supported in the hvqfn48 package. [4] auto?ow control is not supported by channel d of the hvqfn48 package, and this bit should not be written on channel d. [5] the special register set is accessible only when lcr[7] is set to a logic 1. table 9: sc16c554b/554db internal registers a2 a1 a0 register default [1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 general register set [2] 0 0 0 rhr xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 thr xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 ier 00 0 0 0 0 modem status interrupt receive line status interrupt transmit holding register receive holding register 0 1 0 fcr 00 rcvr trigger (msb) rcvr trigger (lsb) reserved reserved dma mode select [3] xmit fifo reset rcvr fifo reset fifo enable 0 1 0 isr 01 fifos enabled fifos enabled 0 0 int priority bit 2 int priority bit 1 int priority bit 0 int status 0 1 1 lcr 00 divisor latch enable set break set parity even parity parity enable stop bits word length bit 1 word length bit 0 1 0 0 mcr 00 0 0 auto?ow control enable [4] loop back op2, intx enable op1 r ts dtr 1 0 1 lsr 60 fifo data error trans. empty trans. holding empty break interrupt framing error parity error overrun error receive data ready 1 1 0 msr x0 cd ri dsr cts d cd d ri d dsr d cts 1 1 1 spr ff bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 special register set [5] 0 0 0 dll xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 dlm xx bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 28 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 7.1 transmit (thr) and receive (rhr) holding registers the serial transmitter section consists of an 8-bit transmit hold register (thr) and transmit shift register (tsr). the status of the thr is provided in the line status register (lsr). writing to the thr transfers the contents of the data bus (d7 to d0) to the thr, providing that the thr or tsr is empty. the thr empty ?ag in the lsr register will be set to a logic 1 when the transmitter is empty or when data is transferred to the tsr. note that a write operation can be performed when the thr empty ?ag is set (logi c 0 = fifo full; logi c 1 = at least one fifo location available). the serial receive section also contains an 8-bit receive holding register (rhr). receive data is removed from the sc16c554b/554db and receive fifo by reading the rhr register. the receive section provides a mechanism to prevent false starts. on the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate. after 7 1 2 clocks, the start bit time should be shifted to the center of the start bit. at this time the start bit is sampled, and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. receiver status codes will be posted in the lsr. 7.2 interrupt enable register (ier) the interrupt enable register (ier) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. these interrupts would normally be seen on the inta to intd output pins in the 16 mode, or on wire-or irq output pin in the 68 mode. table 10: interrupt enable register bits description bit symbol description 7:4 ier[7:4] reserved; set to 0. 3 ier[3] modem status interrupt. logic 0 = disable the modem status register interrupt (normal default condition) logic 1 = enable the modem status register interrupt 2 ier[2] receive line status interrupt. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt 1 ier[1] transmit holding register interrupt. this interrupt will be issued whenever the thr is empty, and is associated with lsr[1]. logic 0 = disable the transmitter empty interrupt (normal default condition) logic 1 = enable the transmitter empty interrupt 0 ier[0] receive holding register interrupt. this interrupt will be issued when the fifo has reached the programmed trigger level, or is cleared when the fifo drops below the trigger level in the fifo mode of operation. logic 0 = disable the receiver ready interrupt (normal default condition) logic 1 = enable the receiver ready interrupt
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 29 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 7.2.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr[0] = logic 1), and receive interrupts (ier[0] = logic 1) are enabled, the receive interrupts and register status will re?ect the following: ? the receive data available interrupts are issued to the external cpu when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. ? fifo status will also be re?ected in the user accessible isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared when the fifo drops below the trigger level. ? the data ready bit (lsr[0]) is set as soon as a character is transferred from the shift register to the receive fifo. it is reset when the fifo is empty. 7.2.2 ier versus receive/transmit fifo polled mode operation when fcr[0] = logic 1, resetting ier[0:3] enables the sc16c554b/554db in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ? lsr[0] will be a logic 1 as long as there is one byte in the receive fifo. ? lsr[1:4] will provide the type of errors encountered, if any. ? lsr[5] will indicate when the transmit fifo is empty. ? lsr[6] will indicate when both the transmit fifo and transmit shift register are empty. ? lsr[7] will indicate any fifo data errors. 7.3 fifo control register (fcr) this register is used to enable the fifos, clear the fifos, set the receive fifo trigger levels, and select the dma mode. 7.3.1 dma mode 7.3.1.1 mode 0 (fcr bit 3 = 0) set and enable the interrupt for each single transmit or receive operation, and is similar to the 16c454 mode. transmit ready ( txrd y) will go to a logic 0 whenever an empty transmit space is available in the transmit holding register (thr). receive ready ( rxrd y) will go to a logic 0 whenever the receive holding register (rhr) is loaded with a character. 7.3.1.2 mode 1 (fcr bit 3 = 1) set and enable the interrupt in a block mode operation. the transmit interrupt is set when there are one or more fifo locations empty. the receive interrupt is set when the receive fifo ?lls to the programmed trigger level. however, the fifo continues to ?ll regardless of the programmed level until the fifo is full. rxrd y remains a logic 0 as long as the fifo ?ll level is above the programmed trigger level.
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 30 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 7.3.2 fifo mode table 11: fifo control register bits description bit symbol description 7:6 fcr[7:6] rcvr trigger. these bits are used to set the trigger level for the receive fifo interrupt. an interrupt is generated when the number of characters in the fifo equals the programmed trigger level. however, the fifo will continue to be loaded until it is full. refer to t ab le 12 . 5:4 fcr[5:4] not used; initialized to logic 0 3 fcr[3] dma mode select. logic 0 = set dma mode 0 (normal default condition) logic 1 = set dma mode 1 transmit operation in mode 0: when the sc16c554b/554db is in the 16c450 mode (fifos disabled; fcr[0] = logic 0) or in the fifo mode (fifos enabled; fcr[0] = logic 1; fcr[3] = logic 0), and when there are no characters in the transmit fifo or transmit holding register, the txrd y pin will be a logic 0. once active, the txrd y pin will go to a logic 1 after the ?rst character is loaded into the transmit holding register. receive operation in mode 0: when the sc16c554b/554db is in mode 0 (fcr[0] = logic 0), or in the fifo mode (fcr[0] = logic 1; fcr[3] = logic 0) and there is at least one character in the receive fifo, the rxrd y pin will be a logic 0. once active, the rxrd y pin will go to a logic 1 when there are no more characters in the receiver. transmit operation in mode 1: when the sc16c554b/554db is in fifo mode (fcr[0] = logic 1; fcr[3] = logic 1), the txrd y pin will be a logic 1 when the transmit fifo is completely full. it will be a logic 0 if one or more fifo locations are empty. receive operation in mode 1: when the sc16c554b/554db is in fifo mode (fcr[0] = logic 1; fcr[3] = logic 1) and the trigger level has been reached, or a receive time-out has occurred, the rxrd y pin will go to a logic 0. once activated, it will go to a logic 1 after there are no more characters in the fifo. 2 fcr[2] xmit fifo reset. logic 0 = no fifo transmit reset (normal default condition) logic 1 = clears the contents of the transmit fifo and resets the fifo counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 1 fcr[1] rcvr fifo reset. logic 0 = no fifo receive reset (normal default condition) logic 1 = clears the contents of the receive fifo and resets the fifo counter logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 0 fcr[0] fifo enable. logic 0 = disable the transmit and receive fifo (normal default condition) logic 1 = enable the transmit and receive fifo. this bit must be a 1 when other fcr bits are written to, or they will not be programmed.
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 31 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 7.4 interrupt status register (isr) the sc16c554b/554db provides four levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with four interrupt status bits. performing a read cycle on the isr will provide the user with the highest pending interrupt level to be serviced. no other interrupts are acknowledged until the pending interrupt is serviced. whenever the interrupt status register is read, the interrupt status is cleared. however, it should be noted that only the current pending interrupt is cleared by the read. a lower level interrupt may be seen after re-reading the interrupt status bits. t ab le 13 interr upt source shows the data values (bits 0 to 5) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. table 12: rcvr trigger levels fcr[7] fcr[6] rx fifo trigger level 001 014 108 1114 table 13: interrupt source priority level isr[5] isr[4] isr[3] isr[2] isr[1] isr[0] source of the interrupt 1 000110 lsr (receiver line status register) 2 000100 rxrdy (receive data ready) 2 001100 rxrdy (receive data time-out) 3 000010 txrdy (transmitter holding register empty) 4 000000 msr (modem status register) table 14: interrupt status register bits description bit symbol description 7:6 isr[7:6] fifos enabled. these bits are set to a logic 0 when the fifo is not being used. they are set to a logic 1 when the fifos are enabled. logic 0 or cleared = default condition 5:4 isr[5:4] reserved; set to 0. 3:1 isr[3:1] int priority bits 2 to 0. these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see t ab le 13 ). logic 0 or cleared = default condition 0 isr[0] int status. logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine logic 1 = no interrupt pending (normal default condition)
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 32 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 7.5 line control register (lcr) the line control register is used to specify the asynchronous data communication format. the word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. table 15: line control register bits description bit symbol description 7 lcr[7] divisor latch enable. the internal baud rate counter latch and enhance feature mode enable. logic 0 = divisor latch disabled (normal default condition) logic 1 = divisor latch enabled 6 lcr[6] set break. when enabled, the break control bit causes a break condition to be transmitted (the tx output is forced to a logic 0 state). this condition exists until disabled by setting lcr[6] to a logic 0. logic 0 = no tx break condition (normal default condition) logic 1 = forces the transmitter output (tx) to a logic 0 for alerting the remote receiver to a line break condition 5 lcr[5] set parity. if the parity bit is enabled, lcr[5] selects the forced parity format. programs the parity conditions (see t ab le 16 ). logic 0 = parity is not forced (normal default condition) lcr[5] = logic 1 and lcr[4] = logic 0: parity bit is forced to a logical 1 for the transmit and receive data lcr[5] = logic 1 and lcr[4] = logic 1: parity bit is forced to a logical 0 for the transmit and receive data 4 lcr[4] even parity. if the parity bit is enabled with lcr[3] set to a logic 1, lcr[4] selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1s in the transmitted data. the receiver must be programmed to check the same format (normal default condition). logic 1 = even parity is generated by forcing an even number of logic 1s in the transmitted data. the receiver must be programmed to check the same format. 3 lcr[3] parity enable. parity or no parity can be selected via this bit. logic 0 = no parity (normal default condition) logic 1 = a parity bit is generated during the transmission, receiver checks the data and parity for transmission errors 2 lcr[2] stop bits. the length of stop bit is speci?ed by this bit in conjunction with the programmed word length (see t ab le 17 ). logic 0 or cleared = default condition 1:0 lcr[1:0] word length bits 1, 0. these two bits specify the word length to be transmitted or received (see t ab le 18 ). logic 0 or cleared = default condition
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 33 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos table 16: lcr[5] parity selection lcr[5] lcr[4] lcr[3] parity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 forced parity 1 1 1 1 forced parity 0 table 17: lcr[2] stop bit length lcr[2] word length (bits) stop bit length (bit times) 0 5, 6, 7, 8 1 15 1 1 2 1 6, 7, 8 2 table 18: lcr[1:0] word length lcr[1] lcr[0] word length (bits) 00 5 01 6 10 7 11 8
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 34 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 7.6 modem control register (mcr) this register controls the interface with the modem or a peripheral device. table 19: modem control register bits description bit symbol description 7:6 mcr[7:6] reserved; set to 0. 5 mcr[5] auto?ow control enable. 4 mcr[4] loop-back. enable the local loop-back mode (diagnostics). in this mode the transmitter output ( tx) and the receiver input ( rx), cts, dsr, cd, and ri are disconnected from the sc16c554b/554db i/o pins. internally the modem data and control pins are connected into a loop-back data con?guration (see figure 14 ). in this mode, the receiver and transmitter interrupts remain fully operational. the modem control interrupts are also operational, but the interrupts sources are switched to the lower four bits of the modem control. interrupts continue to be controlled by the ier register. logic 0 = disable loop-back mode (normal default condition) logic 1 = enable local loop-back mode (diagnostics) 3 mcr[3] op2, intx enable. used to control the modem cd signal in the loop-back mode. logic 0 = forces inta to intd outputs to the 3-state mode during the 16 mode (normal default condition). in the loop-back mode, sets op2 ( cd) internally to a logic 1. logic 1 = forces the inta to intd outputs to the active mode during the 16 mode. in the loop-back mode, sets op2 ( cd) internally to a logic 0. 2 mcr[2] op1. this bit is used in the loop-back mode only. in the loop-back mode, this bit is used to write the state of the modem ri interface signal via op1. 1 mcr[1] r ts logic 0 = force r ts output to a logic 1 (normal default condition) logic 1 = force r ts output to a logic 0 automatic r ts may be used for hardware ?ow control by enabling mcr[5]. 0 mcr[0] dtr logic 0 = force dtr output to a logic 1 (normal default condition) logic 1 = force dtr output to a logic 0
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 35 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 7.7 line status register (lsr) this register provides the status of data transfers between the sc16c554b/554db and the cpu. table 20: line status register bits description bit symbol description 7 lsr[7] fifo data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current fifo data. this bit is cleared when lsr register is read. 6 lsr[6] thr and tsr empty. this bit is the transmit empty indicator. this bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode, this bit is set to 1 whenever the transmit fifo and transmit shift register are both empty. 5 lsr[5] thr empty. this bit is the transmit holding register empty indicator. this bit indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to cpu when the thr interrupt enable is set. the thr bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. the bit is reset to a logic 0 concurrently with the loading of the transmitter holding register by the cpu. in the fifo mode, this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. 4 lsr[4] break interrupt. logic 0 = no break condition (normal default condition) logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo. 3 lsr[3] framing error. logic 0 = no framing error (normal default condition) logic 1 = framing error. the receive character did not have a valid stop bit(s). in the fifo mode, this error is associated with the character at the top of the fifo. 2 lsr[2] parity error. logic 0 = no parity error (normal default condition) logic 1 = parity error. the receive character does not have correct parity information and is suspect. in the fifo mode, this error is associated with the character at the top of the fifo. 1 lsr[1] overrun error. logic 0 = no overrun error (normal default condition) logic 1 = overrun error. a data overrun error occurred in the receive shift register. this happens when additional data arrives while the fifo is full. in this case, the previous data in the shift register is overwritten. note that under this condition, the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. 0 lsr[0] receive data ready. logic 0 = no data in receive holding register or fifo (normal default condition) logic 1 = data has been received and is saved in the receive holding register or fifo
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 36 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 7.8 modem status register (msr) this register provides the current state of the control interface signals from the modem, or other peripheral device to which the sc16c554b/554db is connected. four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a control input from the modem changes state. these bits are set to a logic 0 whenever the cpu reads this register. [1] whenever any msr[3:0] is set to logic 1, a modem status interrupt will be generated. table 21: modem status register bits description bit symbol description 7 msr[7] cd (active high, logical 1). normally this bit is the complement of the cd input. in the loop-back mode this bit is equivalent to the op2 bit in the mcr register. 6 msr[6] ri (active high, logical 1). normally this bit is the complement of the ri input. in the loop-back mode this bit is equivalent to the op1 bit in the mcr register. 5 msr[5] dsr (active high, logical 1). normally this bit is the complement of the dsr input. in loop-back mode this bit is equivalent to the dtr bit in the mcr register. 4 msr[4] cts (active high, logical 1). cts functions as hardware ?ow control signal input if it is enabled via mcr[5]. flow control (when enabled) allows starting and stopping the transmissions based on the external modem cts signal. a logic 1 at the cts pin will stop sc16c554b/554db transmissions as soon as current character has ?nished transmission. normally msr[4] is the complement of the cts input. however, in the loop-back mode, this bit is equivalent to the rts bit in the mcr register. 3 msr[3] d cd [1] logic 0 = no cd change (normal default condition). logic 1 = the cd input to the sc16c554b/554db has changed state since the last time it was read. a modem status interrupt will be generated. 2 msr[2] d ri [1] logic 0 = no ri change (normal default condition). logic 1 = the ri input to the sc16c554b/554db has changed from a logic 0 to a logic 1. a modem status interrupt will be generated. 1 msr[1] d dsr [1] logic 0 = no dsr change (normal default condition). logic 1 = the dsr input to the sc16c554b/554db has changed state since the last time it was read. a modem status interrupt will be generated. 0 msr[0] d cts [1] logic 0 = no cts change (normal default condition). logic 1 = the cts input to the sc16c554b/554db has changed state since the last time it was read. a modem status interrupt will be generated.
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 37 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 7.9 scratchpad register (spr) the sc16c554b/554db provides a temporary data register to store 8 bits of user information. 7.10 sc16c554b/554db external reset conditions 8. limiting values table 22: reset state for registers register reset state ier ier[7:0] = 0 isr isr[7:1] = 0; isr[0] = 1 lcr lcr[7:0] = 0 mcr mcr[7:0] = 0 lsr lsr[7] = 0; lsr[6:5] = 1; lsr[4:0] = 0 msr msr[7:4] = input signals; msr[3:0] = 0 fcr fcr[7:0] = 0 table 23: reset state for outputs output reset state txa, txb, txc, txd high r tsa, r tsb, r tsc, r tsd high dtra, dtrb, dtrc, dtrd high rxrd y high txrd ylow table 24: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 7 v v n voltage at any pin gnd - 0.3 v cc + 0.3 v t amb ambient temperature - 40 +85 c t stg storage temperature - 65 +150 c p tot(pack) total power dissipation per package - 500 mw
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 38 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 9. static characteristics [1] except xtal2, v ol = 1 v typical. [2] refer to t ab le 2 pin descr iption on page 10 for a listing of pins having internal pull-up resistors. table 25: static characteristics t amb = - 40 c to +85 c; tolerance of v cc = 10 %, unless otherwise speci?ed. symbol parameter conditions v cc = 2.5 v v cc = 3.3 v v cc = 5.0 v unit min typ max min typ max min typ max v il(ck) low-level clock input voltage - 0.3 - +0.45 - 0.3 - +0.6 - 0.5 - +0.6 v v ih(ck) high-level clock input voltage 1.8 - v cc 2.4 - v cc 3.0 - v cc v v il low-level input voltage (except xtal1 clock) - 0.3 - +0.65 - 0.3 - +0.8 - 0.5 - +0.8 v v ih high-level input voltage (except xtal1 clock) 1.6 - - 2.0 - - 2.2 - - v v ol low-level output voltage on all outputs [1] i ol =5ma (data bus) --- -----0.4v i ol =4ma (other outputs) --- --0.4---v i ol =2ma (data bus) --0.4------v i ol = 1.6 ma (other outputs) --0.4------v v oh high-level output voltage i oh = - 5ma (data bus) --- ---2.4--v i oh = - 1ma (other outputs) --- 2.0-----v i oh = - 800 m a (data bus) 1.85 - - - - - ---v i oh = - 400 m a (other outputs) 1.85 - - - - - ---v i lil low-level input leakage current -- 10 - - 10 - - 10 m a i cl clock leakage - - 30 - - 30 - - 30 m a i cc supply current f=5mhz --4.5--6--6ma c i input capacitance - - 5 - - 5 - - 5 pf r pu(int) internal pull-up resistance [2] 500 - - 500 - - 500 - - k w
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 39 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 10. dynamic characteristics table 26: dynamic characteristics t amb = - 40 c to +85 c; tolerance of v cc 10 %, unless otherwise speci?ed. symbol parameter conditions v cc = 2.5 v v cc = 3.3 v v cc = 5.0 v unit min max min max min max t 1w , t 2w clock pulse duration 10 - 6 - 6 - ns f xtal oscillator/clock frequency [1] [2] - 48 - 80 80 mhz t 6s address setup time 0 - 0 - 0 - ns t 6h address hold time 0 - 0 - 0 - ns t 7d ior delay from chip select 10 - 10 - 10 - ns t 7w ior strobe width 25 pf load 77 - 26 - 23 - ns t 7h chip select hold time from ior 0- 0- 0- ns t 9d read cycle delay 25 pf load 20 - 20 - 20 - ns t 12d delay from ior to data 25 pf load - 77 - 26 - 23 ns t 12h data disable time 25 pf load - 15 - 15 - 15 ns t 13d io w delay from chip select 10 - 10 - 10 - ns t 13w io w strobe width 20 - 20 - 15 - ns t 13h chip select hold time from io w 0- 0- 0- ns t 15d write cycle delay 25 - 25 - 20 - ns t 16s data setup time 20 - 20 - 15 - ns t 16h data hold time 15 - 5 - 5 - ns t 17d delay from io w to output 25 pf load - 100 - 33 - 29 ns t 18d delay to set interrupt from modem input 25 pf load - 100 - 24 - 23 ns t 19d delay to reset interrupt from ior 25 pf load - 100 - 24 - 23 ns t 20d delay from stop to set interrupt -1t rclk [3] -1t rclk [3] -1t rclk [3] ns t 21d delay from ior to reset interrupt 25 pf load - 100 - 29 - 28 ns t 22d delay from start to set interrupt - 100 - 45 - 40 ns t 23d delay from io w to transmit start 8t rclk [3] 24t rclk [3] 8t rclk [3] 24t rclk [3] 8t rclk [3] 24t rclk [3] ns t 24d delay from io w to reset interrupt - 100 - 45 - 40 ns t 25d delay from stop to set rxrd y -1t rclk [3] -1t rclk [3] -1t rclk [3] ns t 26d delay from ior to reset rxrd y - 100 - 45 - 40 ns t 27d delay from io w to set txrd y - 100 - 45 - 40 ns
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 40 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos [1] applies to external clock, crystal oscillator max 24 mhz. [2] maximum frequency = [3] rclk is an internal signal derived from divisor latch lsb (dll) and divisor latch msb (dlm) divisor latches. 10.1 timing diagrams t 28d delay from start to reset txrd y -8t rclk [3] -8t rclk [3] -8t rclk [3] ns t 30s address setup time 10 - 10 - 10 - ns t 30w chip select strobe width 25 pf load [1] 90 - 26 - 23 - ns t 30h address hold time 15 - 15 - 15 - ns t 30d read cycle delay 25 pf load 20 - 20 - 20 - ns t 31d delay from cs to data 25 pf load - 90 - 26 - 23 ns t 31h data disable time 25 pf load - 15 - 15 - 15 ns t 32s write strobe setup time 10 - 10 - 10 - ns t 32h write strobe hold time 10 - 10 - 10 - ns t 32d write cycle delay 25 - 25 - 20 - ns t 33s data setup time 20 - 15 - 15 - ns t 33h data hold time 15 - 5 - 5 - ns t reset reset pulse width 200 - 40 - 40 - ns n baud rate divisor 1 (2 16 - 1) 1 (2 16 - 1) 1 (2 16 - 1) table 26: dynamic characteristics continued t amb = - 40 c to +85 c; tolerance of v cc 10 %, unless otherwise speci?ed. symbol parameter conditions v cc = 2.5 v v cc = 3.3 v v cc = 5.0 v unit min max min max min max 1 t 3w ------- fig 18. general read timing in 68 mode 002aaa210 t 30s a0 to a4 cs r/w d0 to d7 t 30w t 30h t 30d t 31h t 32s t 31d
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 41 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 19. general write timing in 68 mode 002aaa211 a0 to a4 d0 to d7 cs r/w t 32s t 33s t 33h t 32h t 32d t 30h t 30w t 30s fig 20. general write timing in 16 mode data active active valid address 002aaa171 a0 to a2 cs iow d0 to d7 t 16s t 16h t 13d t 13w t 15d t 6h t 13h t 6s
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 42 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 21. general read timing in 16 mode data active active valid address 002aaa172 a0 to a2 cs ior d0 to d7 t 12d t 12h t 7d t 7w t 9d t 6h t 7h t 6s fig 22. modem input/output timing t 17d change of state t 18d t 18d t 19d 002aaa352 t 18d change of state change of state change of state active active active active active active active change of state rts dtr iow cd cts dsr int ior ri
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 43 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 23. external clock timing external clock 002aaa112 t 3w t 2w t 1w f xtal 1 t 3w ------- = fig 24. receive timing d0 d1 d2 d3 d4 d5 d6 d7 active active 16 baud rate clock 002aaa113 rx int ior t 21d t 20d 5 data bits 6 data bits 7 data bits stop bit parity bit start bit data bits (0 to 7) next data start bit
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 44 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 25. receive ready timing in non-fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab063 next data start bit stop bit parity bit t 25d rx rxrdy ior active data ready start bit data bits (0 to 7) active t 26d fig 26. receive ready timing in fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab064 first byte that reaches the trigger level stop bit parity bit t 25d rx rxrdy ior active data ready start bit data bits (0 to 7) active t 26d
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 45 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 27. transmit timing active transmitter ready active 16 baud rate clock 002aaa116 t 24d int iow active d0 d1 d2 d3 d4 d5 d6 d7 tx 5 data bits 6 data bits 7 data bits stop bit parity bit start bit data bits (0 to 7) next data start bit t 22d t 23d fig 28. transmit ready timing in non-fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab062 stop bit parity bit t 27d tx iow d0 to d7 active transmitter ready start bit data bits (0 to 7) next data start bit byte #1 txrdy t 28d transmitter not ready active
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 46 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 29. transmit ready timing in fifo mode (dma mode 1) d0 d1 d2 d3 d4 d5 d6 d7 002aab061 stop bit parity bit t 27d tx iow d0 to d7 start bit data bits (0 to 7) byte #16 txrdy t 28d fifo full active 5 data bits 6 data bits 7 data bits
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 47 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 11. package outline fig 30. package outline sot314-2 (lqfp64) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 48 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 31. package outline sot315-1 (lqfp80) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o o 0.15 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 sot315-1 136e15 ms-026 00-01-19 03-02-25 d (1) (1) (1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 49 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 32. package outline sot414-1 (lqfp64) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.23 0.13 0.20 0.09 7.1 6.9 0.4 9.15 8.85 0.64 0.36 7 0 o o 0.08 0.08 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot414-1 136e06 ms-026 00-01-19 03-02-20 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.64 0.36 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm sot414-1
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 50 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 33. package outline sot778-3 (hvqfn48) terminal 1 index area terminal 1 index area references outline version european projection issue date iec jedec jeita sot778-3 - - - - - - - - - sot778-3 04-06-16 04-06-23 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included dimensions (mm are the original dimensions) hvqfn48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 6 x 6 x 0.85 mm detail x e h d h l a c a 1 b d e b c a 12 13 24 48 37 1 25 36 e 2 e 1 e e 1/2 e 1/2 e a c b v m c w m y c y 1 x 0 2.5 5 mm scale unit mm 0.05 0.00 0.25 0.15 6.1 5.9 6.1 5.9 3.95 3.65 0.5 0.3 a 1 b 1 a (1) max d (1) e (1) e h 3.95 3.65 d h ee 1 l v 0.1 4.4 e 2 4.4 0.4 c 0.2 w 0.05 y 0.05 y 1 0.1
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 51 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos fig 34. package outline sot188-2 (plcc68) references outline version european projection issue date iec jedec jeita note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. sot188-2 44 60 68 1 9 10 26 43 27 61 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k x y e e b d h e h v m b d z d a z e e v m a pin 1 index 112e10 ms-018 edr-7319 0 5 10 mm scale 99-12-27 01-11-14 plcc68: plastic leaded chip carrier; 68 leads sot188-2 unit b mm 4.57 4.19 0.51 3.3 0.53 0.33 0.021 0.013 1.27 2.16 45 o 0.18 0.1 0.18 dimensions (mm dimensions are derived from the original inch dimensions) 24.33 24.13 25.27 25.02 2.16 0.81 0.66 1.22 1.07 0.180 0.165 0.02 0.13 0.25 0.01 0.05 0.085 0.007 0.004 0.007 1.44 1.02 0.057 0.040 0.958 0.950 24.33 24.13 0.958 0.950 0.995 0.985 25.27 25.02 0.995 0.985 23.62 22.61 0.93 0.89 23.62 22.61 0.93 0.89 0.085 0.032 0.026 0.048 0.042 e e inches d e a a 1 min. a 4 max. b p ey w v d (1) e (1) h d h e z d (1) max. z e (1) max. b 1 k a 3 l p e d e e
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 52 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 12. soldering 12.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 12.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 12.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 53 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 12.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 12.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. table 27: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 54 of 56 philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 13. abbreviations 14. revision history table 28: abbreviations acronym description cpu central processing unit dma direct memory access fifo first in/first out isdn integrated service digital network quart 4-channel (quad) universal asynchronous receiver and transmitter uart universal asynchronous receiver and transmitter table 29: revision history document id release date data sheet status change notice doc. number supersedes sc16c554b_554db_3 20050901 product data sheet - sc16c554b_554db_3 sc16c554b_554db_2 modi?cations: ? figure 6 pin con? gur ation f or lqfp80 on page 8 : corrected names for pins 31 through 40 (pins de?ned in t ab le 2 pin descr iption are correct). ? t ab le 8 baud r ate gener ator prog r amming tab le using a 7.3728 mhz cloc k on page 21 : added (bit/s) to ?rst columns heading ? t ab le 17 lcr[2] stop bit length on page 33 : added (bits) to second columns heading ? t ab le 18 lcr[1:0] w ord length on page 33 : added (bits) to third columns heading sc16c554b_554db_2 20050613 product data sheet - 9397 750 14966 sc16c554b_554db_1 sc16c554b_554db_1 20050209 product data sheet - 9397 750 13133 -
philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos sc16c554b_554db_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 1 september 2005 55 of 56 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 18. trademarks notice all referenced brands, product names, service names and trademarks are the property of their respective owners. 19. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 1 september 2005 document number: sc16c554b_554db_3 published in the netherlands philips semiconductors sc16c554b/554db 5 v, 3.3 v and 2.5 v quad uart, 5 mbit/s (max.) with 16-byte fifos 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.1.1 plcc68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.1.2 lqfp64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1.3 lqfp80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.4 hvqfn48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 6 functional description . . . . . . . . . . . . . . . . . . 15 6.1 interface options . . . . . . . . . . . . . . . . . . . . . . . 16 6.1.1 the 16 mode interface . . . . . . . . . . . . . . . . . . 16 6.1.2 the 68 mode interface . . . . . . . . . . . . . . . . . . 16 6.2 internal registers. . . . . . . . . . . . . . . . . . . . . . . 17 6.3 fifo operation . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 auto?ow control (see figure 9 ) . . . . . . . . . . . . 18 6.4.1 auto- r ts (see figure 9 ). . . . . . . . . . . . . . . . . 18 6.4.2 auto- cts (see figure 9 ). . . . . . . . . . . . . . . . . 18 6.4.3 enabling auto?ow control and auto- cts . . . . 19 6.4.4 auto- cts and auto- r ts functional timing . . . 19 6.5 hardware/software and time-out interrupts. . . 20 6.6 programmable baud rate generator . . . . . . . . 20 6.7 dma operation . . . . . . . . . . . . . . . . . . . . . . . . 22 6.8 loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 22 7 register descriptions . . . . . . . . . . . . . . . . . . . 27 7.1 transmit (thr) and receive (rhr) holding registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 interrupt enable register (ier) . . . . . . . . . . . 28 7.2.1 ier versus receive fifo interrupt mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2.2 ier versus receive/transmit fifo polled mode operation. . . . . . . . . . . . . . . . . . . . . . . . 29 7.3 fifo control register (fcr) . . . . . . . . . . . . . 29 7.3.1 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3.1.1 mode 0 (fcr bit 3 = 0) . . . . . . . . . . . . . . . . . . 29 7.3.1.2 mode 1 (fcr bit 3 = 1) . . . . . . . . . . . . . . . . . . 29 7.3.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 interrupt status register (isr) . . . . . . . . . . . . 31 7.5 line control register (lcr) . . . . . . . . . . . . . . 32 7.6 modem control register (mcr) . . . . . . . . . . . 34 7.7 line status register (lsr) . . . . . . . . . . . . . . . 35 7.8 modem status register (msr). . . . . . . . . . . . 36 7.9 scratchpad register (spr) . . . . . . . . . . . . . . 37 7.10 sc16c554b/554db external reset conditions 37 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 37 9 static characteristics . . . . . . . . . . . . . . . . . . . 38 10 dynamic characteristics . . . . . . . . . . . . . . . . . 39 10.1 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 40 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 47 12 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.2 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 52 12.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 52 12.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 53 12.5 package related soldering information . . . . . . 53 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 54 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 54 15 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 55 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 18 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 19 contact information . . . . . . . . . . . . . . . . . . . . 55

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